linux - Secure mode can access secure / non secure memory how? -
According to the Cortex Contractor Guide
TrustZone hardware also effectively provides two virtual MMUs, one for each virtual processor
The page table description contains an NS bit, which is used to determine whether the access is in a secure or non-secure physical address space.
Although the page table entry bit still exists, normal virtual processor hardware does not use this field, and memory access is always created with NS = 1. Secure Virtual Processor can therefore access secure or normal memory. Cache and TLB hardware allow for general and secure entries for co-existence.
So, if a code (to be running in safe mode) should be written to access, then the address can be coded to 0xA0000000 [Ns] and 0xA0000000 [S] how?
So if a code (to run in safe mode) is to be used to address address 0xA0000000 [ns] And 0xA0000000 [S] How will it be coded?
It is possible that you have a conceptual issue here. There is no physical address 0xA0000000 [ns] and 0xA0000000 [s] , there is only physical address 0xA0000000 . The
ns bit is used by the bus controller, such asHPROT (user / supervisor) access permission on access ; Later, only a physical memory stores the result. In this way, the SDRAM device does not need to be aware of trustzone , but just the controllerYou need to setup the world to be shareable Mapping is the facility to read / write in both worlds, then it applies as information if both OS If MMU is, then create two mapping with the same physical address. Two copies of memory and MMU entries can be present in L1-Cash and TLB. There is no problem with duplicate TLB, after writing this memory, L1 might require flushing, there will be two lines with the same data, but one more one tagged with
nsThere may be an interesting paper in this context.
Comments
Post a Comment